Configuration Code Generation and Optimizations for Heterogeneous Reconfigurable Dsps
نویسندگان
چکیده
In this paper we describe a code generation and optimization process for reconfigurable architectures targeting digital signal processing and wireless communication applications. The ability to generate efficient and compact code is essential for the success of reconfigurable architectures. Otherwise, the overhead of reconfiguring could easily become the system bottleneck. Our code generation process includes the evaluation a set of tradeoffs in system design, software engineering as well as usage of a set of local and global optimization techniques. By doing so we are able to achieve results of significantly lower overhead.
منابع مشابه
A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems
This paper presents a high level, machine independent, algorithmic, singleassignment programming language SA-C and its optimizing compiler targeting recongurable systems, and intended for Image Processing applications. Language features are introduced and discussed. The intermediate forms DDCF and DFG, used in the optimization and code-generation phases are described. Conventional and recon gur...
متن کاملA retargetable VLIW compiler framework for DSPs withinstruction-level parallelism
A standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the diff...
متن کاملOptimization of embedded DSP programs using post-pass data-flow analysis
We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limited quantity of silicon to program ROM, so application software must be maximally dense. Additionally, the software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, current compiler technology is unable to generate den...
متن کاملReconfigurable Instruction Set Processors from a Hardware/Software Perspective
This paper presents the design alternatives for reconfigurable instruction set processors (RISP) from a hardware/software point of view. Reconfigurable instruction set processors are programmable processors that contain reconfigurable logic in one or more of its functional units. Hardware design of such a type of processors can be split in two main tasks: the design of the reconfigurable logic ...
متن کاملGreedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs
VLIW DSP architectures can have heterogeneous connections between functional units and register files for speeding up special tasks. Such architectural characteristics can be effectively exploited through the use of complex instruction set extensions (ISEs). Although VLIWs are increasingly being used for DSP applications to achieve very high performance, such architectures are known to suffer f...
متن کامل